A variety of techniques are used to stack integrated circuits. Some require that the circuits be encapsulated in special packages, while others use circuits in conventional packages. Both leaded and BGA type packaged integrated circuits (ICs) have been stacked. Although BGA packaging becoming widely adopted, leaded packages are still employed in large volumes in low cost applications such as, for example, flash memory which is typically packaged in thin small outline packages otherwise known as TSOPs.
When leaded packages such as TSOPs are stacked, a variety of techniques have been employed. In some cases, the leads alone of packaged circuits have been used to create the stack and interconnect its constituent elements. In other techniques, structural elements such as printed circuit boards (PCBs) are used to create the stack and interconnect the constituent elements.
Circuit boards and rail-like structures in vertical orientations have been used for years to provide interconnection between stack elements. For example, in U.S. Pat. No. 5,514,907 to Moshayedi, a technique is described for creating a multi-chip module from surface-mount packaged memory chips. The devices are interconnected on their lead emergent edges through printed circuit boards oriented vertically to a carrier or motherboard that is contacted by connective sites along the bottom of the edge-placed PCBs. The PCBs have internal connective rail-like structures or vias that interconnect selected leads of the upper and lower packaged memory chips. Japanese Patent Laid-open Publication No. Hei 6-77644 discloses vertical PCBs used as side boards to interconnect packaged circuit members of the stack. In U.S. Pat. No. 5,266,834 to Nishi et al., one depicted embodiment illustrates a stack created by selective orientation of the leads of particularly configured stack elements, while in U.S. Pat. No. 5,343,075 to Nishino, a stack of semiconductor devices is created with contact plates having connective lines on inner surfaces to connect the elements of the stack. Another technique for stacking leaded packaged ICs with carrier structures or interposers oriented along lead bearing sides of packaged devices such as TSOPs is disclosed by the present assignee, Staktek Group L.P., in U.S. Pat. No. 6,608,763 to Burns et al.
Many of the previously cited and known techniques for using PCBs and similar interposer structures for stacking leaded packaged devices have evolved to meet the increased connective complexity presented by, for example, stacking memory components that have two chip enables per packaged device. In some cases, this evolution has included use of interposer designs that employ four layer designs to implement the more complex connection strategies required by more complex devices. This has led to complexities in via and connection strategies, however.
Higher layer count PCBs and similar interposers are more expensive and difficult to produce than simpler designs with fewer layers. Such connective elements also typically exhibit wider variations across the population. What is needed, therefore, is a system and method for stacking leaded packaged devices that implements more complex connection strategies with reduced layer counts in technologies that are easily understood and implemented with known techniques and materials but still meet profile requirements at the surface of the circuit board.